In this paper, we analyze the variability of III-V homojunction tunnel FET\n(TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in\nnear-threshold region. The impacts of the most severe intrinsic device variations including\nwork function variation (WFV) and fin line-edge roughness (fin LER) on TFET and\nFinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are\ninvestigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo\nsimulations and HSPICE simulations with look-up table based Verilog-A models\ncalibrated with TCAD simulation results. The results indicate that WFV and fin LER have\ndifferent impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA\ncircuit delay and power-delay product (PDP) of TFET are significantly better than FinFET\ndue to its better Ion and Cg,ave and their smaller variability. However, the leakage power of\nTFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.
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